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sd-14595/96/97 synchro/resolver-to-digital converters description the sd-14595 is a low-cost, high reliability, synchro- or resolver-to-dig- ital converter with 14-bit-only, 16-bit- only or pin programmable 14-bit or 16-bit resolution. packaged in a 36- pin ddip, the sd-14595/96/97 series feature built-in-test (bit) output. the sd-14595/96/97 series accepts broadband inputs: 360 to 1 khz. other features are solid-state signal and ref- erence isolation and high common mode rejection. in addition, the sd- 14596 and sd-14597 are pin-for-pin replacements for the natel 1044 and 1046, respectively. the digital angle output from the sd-14595/96/97 is a natural binary code, parallel positive logic and is ttl/cmos compatible. the sd- 14595/96/97 accomplishes synchro- nization to a computer with the converter busy (cb) output and/or the inhibit (inh) input. applications because of its high reliability, small size, and low power consumption, the sd-14595/96/97 is ideal for military ground or avionics applications. all models are available with mil-prf- 38534 processing. designed with three-state output, the sd-14595/96/97 is especially well- suited for use with computer based systems. among the many possible applications are radar and navigation systems, fire control systems, flight instrumentation, and flight trainers or simulators. features ? single +5 v power supply ? accuracy to 1.3 arc minutes ? pin programmable 14 bit/16 bit, 14 bit only or 16 bit only ? no 180 false lock-up ? internal synthesized reference ? built-in-test (bit) output ? low power ? pin-for-pin replacement for natels 1044 and 1046 high accuracy control transformer gain demodulator error processor vco 16 bit up/down counter u t vel d sin ( q - f ) e sin q cos q 3 state ttl buffer 3 state ttl buffer voltage doubler inhibit transparent latch 16 bit ct transparent latch 16 bit output transparent latch edge triggered latch digital angle f q +8.6 v inh bits 1-8 hbe 50 ns delay resolution control 1 lsb antijitter feedback los synthesized ref reference conditioner bit detect rh rl ref in los analog return v(+4.3 v) v +5 v 14b lbe bits 9-16 t t u inh r e cb vel e bit (14595 only) s1 s2 s3 solid state synchro input option electronic scott t sin q cos q s1 s2 s3 solid state resolver input option resolver conditioner sin q cos q s4 direct input option voltage follower buffer sin q cos q sin q cos q input options v internal dc reference input option ? 1997, 1999 data device corporation figure 1. sd-14595/96/97 block diagram
2 sd-14595/96/97 specifications specifications apply over temperature range, power supply range, ref- erence frequency, and amplitude range; 15% signal amplitude varia- tion, up to 10% harmonic distortion in the reference, and up to 45 of signal to reference phase shift. parameter unit value resolution bits 14 or 16 repeatabilty lsb 1 max reference input characteristics carrier frequency range voltage range input impedance: n single ended n differential common mode range hz hz vrms ohm ohm v accuracy min 5.2, 2.6, or 1.3 digital input/output logic type inputs: inhibit (inh) signal input characteristics (voltage options and minimum input impedance) input impedance imbalance n synchro ? zin line-to-line ? zin each line-to-gnd ? common mode range ? maximum transient peak voltage n resolver ? zin single ended ? zin differential ? zin each line-to gnd ? common mode range ? maximum transient peak voltage n direct (1.0 v l-l) ? input signal type ? sin/cos voltage range ? max voltage w/o damage ? input impedance reference synthesizer sig/ref phase shift 0.2 max 11.8 v l-l 90 v l-l 17.5k 130k 11.5k 85k 30 180 150 11.8 v l-l 23k 46k 23k 60 max 150 sin and cos resolver sig- nals referenced to converter internal dc reference v. 1 v nominal, 1.15 v max 15 v continuous 100 v peak transient zin > 20m // 10 pf voltage follower 60 typ, 45 guaranteed ttl/cmos compatible logic 0 = 0.8 v max logic 1 = 2.0 v min loading = 30 a max logic 0 inhibits data stable within 0.5 s (pull up) 47-1000 (60 hz unit) 360-1000 (400 hz unit) 4-130 (for 11.8 v or 90 v sig- nal input) 3-100 (for 1 v direct signal input) 250k min 500k min 250 peak max % v ohm ohm vpeak v v ohm ohm ohm v v vrms ohm deg parameter unit value digital input/output (cont) resolution control (14b) (for programmable units only) enable bits 1 to 8 (hbe) enable bits 9 to 16 (lbe) (9 to 14 for 14-bit mode) outputs: parallel data converter busy (cb) bit drive capability bits logic 1 for 14 bits logic 0 for 16 bits pull-up current source to +5 v//5 pf max cmos transient protected logic 0 enables data valid within 150 ns logic 1 = high z data high z within 100 ns pull-down current source to gnd//5 pf max cmos transient protected 14 or 16 parallel lines; natural binary angles, posi- tive logic (see table 3) 0.8 to 3.0 s positive pulse; leading edge initiates counter update. logic 1 for fault conditions. 50 pf + rated logic drive logic 0; 1 ttl load, 1.6 ma at 0.4 v max logic 1; 10 ttl loads, 0.4 ma at 2.8 v min high z;10 a//5 pf max logic 0; 100 mv max driving cmos logic 1; +5 v supply minus 100 mv min driving cmos dynamic characteristics see table 6 physical characteristics in (mm) oz(g) .9 x 0.78 x 0.21 (48 x 20 x 5.3 ) 36-pin double dip 0.7 max (20) temperature ranges operating (-1xx or -4xx) (-3xx or -8xx) storage c c c -55 to +125 0 to 70 -65 to +150 power supply characteristics nominal voltage voltage tolerance max voltage w/o damage current v % v ma +5 10 +7 25 max+digital output load table 1. sd-14595/96/97 specifications (cont) analog output analog return (v) velocity (vel) (see note 3.) ac error (e) n 14-bit mode n 16-bit mode load mv rms mv rms ma +4.3 v nom see table 4. 3.5 per lsb of error 1.75 per lsb of error 1
3 synchroz in (z so ) resolverz in 180 w 100 k w - 30 k w 20 k w 30 k w 47 - 440 hz 80 -138 v rms; 115 v rms nominal resistive 600 k w min, resistive 500 v rms transformer isolated +r (in phase with rh-rl) and -r (in phase with rl- rh) derived from op-amps. short-circuit proof. 3.0 v nominal riding on ground reference v. output voltage level tracks input level. 4 ma typ, 7 ma max from +15 v supply. 47 - 440 hz 10 -100 v rms l- l; 90 v rms l- l nominal 148 k w min l- l balanced resistive 500 v rms, transformer isolated resolver output, - sine (- s) + cosine (+c) derived from op-amps. short circuit proof. 1.0 v rms nominal riding on ground reference v. output voltage level tracks input level. 4 ma typ, 7 ma max from +15 v supply. 360 - 1000 hz 18 - 130 v 40 k w min 1200 v peak 360-1000 hz 700 v peak parameter value notes: (1) pin programmable. (2) see table 7. (3) vel polarity is negative volltage for positive angular rate minimum input impedances (balanced) 90 v l-l 26 v l-l 11.8 v l-l 60 hz transformers reference transformer carrier frequency range input voltage range input impedance input common mode voltage output description output voltage power required signal transformer carrier frequency range input voltage range input impedance input common mode voltage output description output voltage power required table 1. sd-14595/96/97 specifications (contd) theory of operation the sd-14595/96/97 series are small, 36-pin ddip synchro-to- digital hybrid converters. as shown in the block diagram (fig- ure 1), the sd-14595/96/97 can be broken down into the fol- lowing functional parts: signal input option, converter, analog conditioner, power supply conditioner, and digital interface. converter operation as shown in figure 1, the converter section of the sd- 14595/96/97 contains a high accuracy control transformer, demodulator, error processor, voltage controlled oscillator (vco), up-down counter, and reference conditioner. the con- verter produces a digital angle which tracks the analog input angle to within the specified accuracy of the converter.the con- trol transformer performs the following trigonometric computa- tion: sin( q - f ) = sin q cos f - cos q sin f where: q is angle theta representing the resolver shaft position. f is digital angle phi contained in the up/down counter. the tracking process consists of continually adjusting f to make ( q - f ) = 0, so that f will represent the shaft position q . the output of the demodulator is an analog dc level proportional to sin( q - f ). the error processor receives its input from the demodulator and integrates this sin( q - f ) error signal which then drives the vco. the vcos clock pulses are accumulated by the up/down counter. the velocity voltage accuracy, linearity and off- set are determined by the quality of the vco. functionally, the up/down counter is an incremental integrator. therefore, there are two stages of integration which makes the converter a type ii tracking servo. in a type ii servo, the vco always settles to a counting rate which makes d f /dt equal to d q /dt without lag. the output data will always be fresh and available as long as the maximum tracking rate of the converter is not exceeded. the reference conditioner is a comparator that produces the square wave reference voltage which drives the demodulator. its single ended input z is 250k ohms/min, 500k ohms differential. special functions reference synthesizer-quadrature voltages. the synthesized reference section of the sd-14595 eliminates errors caused by quadrature voltage. due to the inductive nature of synchros and resolvers, their signals typically lead the refer- ence signal (rh and rl) by about 6. when an uncompensated reference signal is used to demodulate the control transformers output, quadrature voltages are not completely eliminated. in a 14-bit converter it is not necessary to compensate for the refer- ence signals phase shift. a 6 phase shift will, however, cause problems for the one minute accuracy converters. as shown in figure 1, the converter synthesizes its own cos( w t + a ) refer- transformer characteristics (see ordering information for list of transformers. reference transformers are optional for both solid-state and voltage follower input options.) 400 hz transformers reference transformer carrier frequency range voltage range input impedance breakdown voltage to gnd signal transformer carrier frequency range breakdown voltage to gnd
bit will also be set for a loss-of-signal (los) and/or a loss-of- reference (lor). programmable resolution (14b, pin 16) resolution is controlled by one logic input,14b. the resolution can be changed during converter operation so the appropriate resolution and velocity dynamics can be changed as needed. to insure that a race condition does not exist between counting and changing the resolution, input 14b is latched internally on the trailing edge of cb (see figure 2). note: the sd-14595 has programmable resolution whereas the sd-14596 and 97 do not. interfacing - inputs signal input options the sd-14595/96/97 series offers direct synchro or resolver inputs. in a synchro or resolver, shaft angle data is transmitted as the ratio of carrier amplitudes across the input terminals. synchro signals, which are of the form sin q cos w t, sin( q +120) cos w t, and sin( q +240)cos w t are internally converted to resolver format, sin q cos w t and cos q cos w t. figure 3 illustrates synchro and resolver signals as a function of the angle q . the solid-state signal and reference inputs are true differential inputs with high ac and dc common mode rejection. input imped- ance is maintained with power off. 4 ence signal from the sin q - cos( w t + a ), cos q - cos( w t + a ) signal inputs and from the cos w t reference input. the phase angle of the synthesized reference is determined by the signal input. the reference input is used to choose between the +180 and -180 phases. the synthesized reference will always be exactly in phase with the signal input, and quadrature errors will therefore be eliminated. the synthesized reference circuit also elimi- nates the 180 false error null hangup. quadrature voltages in a resolver or synchro are by definition the resulting 90 fundamental signal in the nulled out error voltage (e) in the converter. a digital position error will result due to the interaction of this quadrature voltage and a reference phase shift between the converter signal and reference inputs. the magni- tude of this error is given by the following formula: magnitude of error=(quadrature voltage/full scale (fs).signal) ? tan( a ) where: magnitude of error is in radians. quadrature voltage is in volts. full scale signal is in volts. a = signal to ref phase shift an example of the magnitude of error is as follows: let: quadrature voltage = 11.8 mv let: fs signal = 11.8 v let: a = 6 then: magnitude of error = 0.35 min @ 1 lsb in the 16th bit. note: quadrature is composed of static quadrature which is specified by the synchro or resolver supplier plus the speed volt- age which is determined by the following formula: speed voltage=(rotational speed/carrier frequency) ? fs signal where: speed voltage is the quadrature due to rotation. rotational speed is the rps (rotations per second) of the synchro or resolver. carrier frequency is the ref in hz. built-in-test (bit, pin 15) the built-in-test output (bit) monitors the level of error (d) from the demodulator. d represents the difference in the input and output angles and ideally should be zero. if it exceeds approxi- mately 180 lsbs (of the selected resolution) the logic level at bit will change from a logic 0 to logic 1. this condition will occur during a large step and reset after the converter settles out. bit will also change to logic 1 for an over-velocity condition, because the converter loop cannot maintain input-output and/or if the con- verter malfunctions where it cannot maintain the loop at a null. 14b 0 m s min cb 0.1 m s min 30 90 150 210 270 330 360 q (degrees) ccw in phase with rl-rh of converter and r2-r1 of cx. 0 s1-s3 = v sin q max s3-s2 = v sin( q + 120) max s2-s1 = v sin( q + 240) max - v max + v max 30 90 150 210 270 330 360 q (degrees) ccw in phase with rh-rl of converter and r2-r4 of rx. 0 s2-s4 = v cos q max s1-s3 = v sin( q) max - v max + v max figure 2. resolution control timing diagram standard resolver control transmitter (rx) outputs as a function of ccw rotation from electrical zero (ez) with r2-r4 excited. standard synchro control transmitter (cx) outputs as a function of ccw rotation from electrical zero (ez). figure 3. synchro and resolver signals
5 solid-state buffer input protection transient voltage suppression the solid-state signal and reference inputs are true differential inputs with high ac and dc common rejection, so most applica- tions will not require units with isolation transformers. input impedance is maintained with power off. the recurrent ac peak + dc common mode voltage should not exceed the values in table 2. reference oscillator parallel data sd-14595/96/97 stator rotor s3 s1 s2 s2 s1 s3 lbe hbe r2 r1 lo hi rh vel (velocity) inh (inhibit) cb (count) rl s4 reference oscillator parallel data stator rotor s3 s1 s2 s2 s1 s3 lbe hbe r4 r2 lo hi rh vel (velocity) inh (inhibit) cb (count) rl s4 s4 rd-14595/96/97 figure 4. synchro input connection diagram figure 5. resolver input connection diagram 90 v line-to-line systems may have voltage transients which exceed the 500 v specification listed. these transients can destroy the thin-film input resistor network in the hybrid. therefore, 90 v l-l solid-state input modules may be protected by installing voltage suppressors as shown. voltage transients are likely to occur whenever synchro or resolver are switched on and off. for instance a 1000 v transient can be generated when the primary of a cx or tx driving a synchro or resolver input is opened. see figure 6. interfacing - digital outputs and controls digital interface the digital interface circuitry performs three main functions: 1. latches the output bits during an inhibit (inh) command allow- ing stable data to be read out of the sd-14595/96/97. 2. furnishes parallel tri-state data formats. 3. acts as a buffer between the internal cmos logic and the external ttl logic. in the sd-14595/96/97, applying an inhibit (inh) command will lock the data in the inhibit transparent latch without interfering with the continuous tracking of the converters feedback loop. therefore the digital angle f is always updated and the inh can be applied for an arbitrary amount of time. the inhibit transparent latch and the 50 ns delay are part of the inhibit cir- cuitry. for further information see the inhibit (inh, pin 13) paragraph. hybrid s3 s2 s1 rh rl cr1 cr2 s1 for 90 v synchro inputs 1n6071a cr3 s2 s3 cr1, cr2, and cr3 are 1n6136a, bipolar transient voltage suppressors or equivalent. hybrid s3 s2 s1 s4 for 90 v resolver inputs cr4 cr5 s3 s2 s1 s4 90 v l-l resolver input cr4 and cr5 are 1n6136a, bipolar transient voltage suppressors or equivalent. figure 6. connections for voltage transient suppressors common mode maximum 100 v 30 v peak 180 v peak 250 v peak 150 v 150 v 150 v 11.8 vl-l 90 vl-l reference max transient peak voltage 1 vl-l input table 2.
6 updated, cb is at logic 0 and the inh latch is transparent; when cb goes to logic 1, the inh latch is locked. if cb occurs after inh has been applied, the latch will remain locked and its data will not change until cb returns to logic 0; if inh is applied during cb, the latch will not lock until the cb pulse is over. the purpose of the 50 ns delay is to prevent a race condition between cb and inh where the up-down counter begins to change as an inh is applied. an inh input, regardless of its duration, does not affect the con- verter update. a simple method of interfacing to a computer asynchronous to cb is: (1) apply inh; (2) wait 0.5 m s min; (3) transfer the data; (4) release inh (see figure 9). a logic 1 for the inh enables the output data to be updated. the time it takes for inh to go to a logic 1 should be 100 ns minimum before valid data is transferred. to allow the update of the output data with valid information the inh must remain at a logic 1 for 1 m s minimum (see figure 10 below). digital angle outputs (logic input/output) the digital angle outputs are buffered and provided in a two-byte format. the first byte contains the msbs (bits 1-8) and is enabled by placing hbe (pin 35) to a logic 0. depending on the user pro- grammed resolution, the second byte contains the lsbs and is enabled by placing lbe (pin 17) to a logic 0. the second byte will contain either bits 9-14 (14-bit resolution) or bits 9-16 (16-bit resolution). all unused lsbs will be at logic 0. table 3 lists the angular weight for the digital angle outputs. the digital angle outputs are valid 150 ns after hbe or lbe are activated with a logic 0 and are high impedance within 100 ns max after hbe and lbe are set to logic 1 (see figure 7). both enables are internally pulled down. digital angle output timing the digital angle output is 14 or 16 parallel data bits and converter busy (cb). all logic outputs are short-circuit proof to ground and +5 v. the cb output is a positive, 0.8 to 3.0 m s pulse. the digital output data changes approximately 50 ns after the leading edge of the cb pulse because of an internal delay. data is valid 0.2 m s after the leading edge of cb (see figure 8). the angle is determined by the sum of the bits at logic 1. the digital outputs are valid 150 ns max after hbe or lbe go low and are high impedance within 100 ns max of hbe or lbe going high. inhibit (inh, pin 13) when an inhibit (inh) input is applied to the sd-14595/96/97, the output transparent latch is locked causing the output data bits to remain stable while data is being transferred (see fig- ure 9). the output data bits are stable 0.5 m s after inh goes to logic 0. a logic 0 at the input of the inhibit transparent latch latches the data, and a logic 1 applied, allows the bits to change. this latch also prevents the transmission of invalid data when there is an overlap between cb and inh. while the counter is not being depends on d f /dt 0.8-3.0 m s cb 0.2 m s data valid 6.1 m s min 0.5 s inh 100 ns min data update stable stable 1 s min data valid 0.5 m s asynchrous to cb inh 100 ns max hbe or lbe 150 ns min output valid high z high z figure 8. converter busy timing diagram figure 7. tri-state output timing figure 10. output data update timing figure 9. inhibit timing diagram table 2. digital angle outputs bit deg/bit min/bit 1(msb) 2 3 4 5 6 7 8 9 10 11 12 13 14(lsb 14 bit mode) 15 16(lsb 16 bit mode) 180 90 45 22.5 11.25 5.625 2.813 1.405 0.7031 0.3516 0.1758 0.0879 0.0439 0.0220 0.0110 0.0055 10800 5400 2700 1350 675 337.5 168.75 84.38 42.19 21.09 10.55 5.27 2.64 1.32 0.66 0.33 note: hbe enables the 8 msbs and lbe enables the lsbs.
interfacing - digital outputs and controls (contd) data transfers digital output data from the sd-14595/96/97 can be transferred to 8-bit and 16-bit bus systems. for 8-bit systems, the msb and lsb bytes are transferred sequentially. for 16-bit systems all bits are transferred at the same time data transfer to 8-bit bus figures 11 and 12 show the connections and timing for trans- ferring data from the sd-14595/96/97 to an 8-bit bus. as can be seen by the timing diagram, the following occurs: 1. the converter inh control is applied and must remain low for a minimum of 500 ns before valid data is transferred. 2. hbe is set to a low state (logic 0) 350 ns min after inh goes low and must remain low for a minimum of 150 ns before the msb data (1-8) is valid and transferred. 3. as hbe is set to a high state (logic 1), lbe is brought low for a 150 ns min before the lsb data is valid and transferred. 4. lbe should go high (to logic 1) at least 100 ns max before another device uses the bus. 5.setting inh high when data transfer is done, the data refresh cycle can begin. note the time it takes for inh to go to a logic 1 should be 100 ns minimum before valid data is transferred. note: for further understanding, refer to the beginning of this section (digital interface, digital angle outputs, digital angle output timing, and inhibit). 16-bit data transfer data transfer to the 16-bit bus is much simpler than the 8-bit bus. figures 13 and 14 (page 8) show the connections and timing for transferring data from the sd-14595/96/97 to a 16-bit bus. as can be seen by the timing diagram the following occurs: 1. the converter inh control is applied and must remain low for a minimum of 500 ns before valid data is transferred. 2. hbe and lbe are set to a low state (logic 0) 350 ns min after inh goes low and must remain low for a minimum of 150 ns before the data (1-16) is valid and transferred. 3. hbe and lbe should go high (to logic 1) at least 100 ns max before another device uses the bus. 4. inh goes high and data transfer is done and the data refresh cycle can begin. note the time it takes for inh to go to a logic 1 should be 100 ns minimum before valid data is transferred. note: for further understanding, refer to the beginning of this section (digital interface, digital angle outputs, digital angle output timing, and inhibit). 7 sd-14595/96/97 8-bit bus (msb) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 (lsb) bit 16 d7 d6 d5 d4 d3 d2 d1 d0 hbe lbe inh inh data 1-8 valid data 9-16 valid 500 ns min 150 ns min 0 ns min 100 ns max 150 ns min 0 ns min 100 ns max lbe hbe figure 11. data transfer to 8-bit bus figure 12. data transfer to 8-bit bus timing
interfacing - analog outputs the analog outputs are ac error (e), analog return (v), and velocity (vel). ac error (e, pin 12) the ac error is proportional to the difference between the input angle q and the digital input angle f, ( q - f ), with a scaling of: 3.5 mv rms/lsb (14-bit mode) 1.75 mv rms/lsb (16-bit mode) the e output can swing 3 v min with respect to analog return (v). analog return (v, pin 11) this internal voltage is not required externally for normal opera- tion of the converter. it is used as the internal dc reference and the return for the vel and e outputs. it is nominally +4.3 v and is proportional to the +5 v dc supply. velocity (vel, pin 10) the velocity output (vel, pin 10) is a dc voltage proportional to angu- lar velocity d q /dt. the velocity is the input to the voltage controlled oscillator (vco), as shown in figure 1. its linearity and accuracy is dependent solely on the linearity and accuracy of the vco. the vel output can swing 1.10 v with respect to analog return (v). the analog output vel characteristics are listed in tables 4 and 5. the vel output has dc tachometer quality specs such that it can be used as the velocity feedback in servo applications. 8 table 4. velocity characteristics parameter units typ max polarity vel is negative for positive angular rate. device type output voltage (see note) v 400 hz 60 hz 1.1 1.1 400 hz 60 hz 1.1 1.1 voltage scaling rps/1.1 v see vel. voltage scaling table 5. scale factor error reversal error linearity error zero offset load 10 1 0.5 5 0.5 10 1 0.5 5 0.5 15 2 1 20 0.5 15 2 1 20 0.5 note: with respect to analog return (v) table 5. velocity voltage scaling (values in v/rps) 14 bit device type 16 bit 0.11 0.56 400 hz 60 hz 0.44 2.23 note: if the resolution is changed while the input is changing, then the velocity output voltage and the digital output will have a transient until it settles to the new velocity scaling at a speed determined by the bandwidth. 16-bit bus (msb) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 (lsb) bit 16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hbe lbe inh sd-14595/96/97 inh data 1-16 valid 500 ns min 150 ns min 0 ns min 100 ns max hbe, lbe figure 14. 16-bit data transfer timing figure 13. 16-bit data transfer % % % output mv ma
interfacing - dynamic performance a type ii servo loop (k v = ) and very high acceleration con- stants give the sd-14595/96/97 superior dynamic performance. if the power supply voltage is not the +5 v dc nominal value, the specified input rates will increase or decrease in proportion to the fractional change in voltage. transfer functions the dynamic performance of the converter can be determined from its transfer function block diagram (figure 15) and open and closed loop bode plots (figures 16 and 17). values for the transfer function block can be obtained from table 6. 9 error processor input q open loop transfer function = output where: 2 a = a a 1 2 velocity out digital position out ( f ) vco ct s a + 1 1 b s s + 1 10b h = 1 2 s a + 1 b 2 s s + 1 10b + - e a 2 s -12 db/oct 4 ba (bw) 2a -6 db/oct 10b w (rad/sec) 2a 2 2 a w (rad/sec) closed loop bw (hz) = 2 a p figure 17. closed loop bode plot figure 16. open loop bode plot figure 15. transfer function block diagram response parameters as long as the converter maximum tracking rate is not exceed- ed, there will be no velocity lag in the converter output although momentary acceleration errors remain. if a step input occurs, as when the power is initially applied, the response will be critically damped. figure 18 shows the response to a step input. after initial slewing at the maximum tracking rate of the converter, there is one overshoot (which is inherent in a type ii servo). the overshoot settling to a final value is a function of the small signal settling time. faster settling time using bit to reduce resolution since the sd-14595 has higher precision in the 16-bit mode and faster settling in the 14-bit mode, the bit output can be used to program the sd-14595 for lower resolution, allowing the con- verter to settle faster for step inputs. high precision, faster set- tling can therefore be obtained simultaneously and automatical- ly in one unit. connecting the sd-14595/96/97 to a p.c. board the sd-14595/96/97 can be attached to a printed circuit board using hand solder or wave soldering techniques. limit exposure to 300c (572f) max, for 10 seconds maximum. since the sd-14595/96/97 converters contain a cmos device, standard cmos handling procedures should be fol- lowed. table 6. dynamic characteristics 60 hz unit 400 hz unit 16-bit parameter unit 14-bit 14-bit input freq. tracking rate bandwidth, cl ka a1 a2 a b acc-1 lsb lag settling time 180 degree step 1.4 degree step hertz rps hertz 1/sec 1/sec 1/sec 1/sec 1/sec /sec ms ms 47-1k 1.5 40 7,680 0.1 40k 88 14.2 169 450 100 360-1k 10 320 192,000 1.2 160,000 440 100 4220 100 10 16-bit 47-1k 0.5 20 1920 0.045 40k 44 14.2 11 2000 250 overshoot small signal settling time max slope equals tracking rate (slew rate) q 2 q 1 settling time figure 18. response to step input 360-1k 2.5 110 48,000 0.3 160,00 0 220 100 264 400 30
10 1.900 max (48.26 max) 1.700 0.005 (43.2 0.13) 0.018 (0.46) diam typ 0.100 typ(2.54) tol. non- cumulative 0.21 max (5.3) 0.800 max (20.3 max) 0.600 0.005 (15.2 0.13) contrasting colored bead identifies pin 1 side view bottom view 0.24 min (6.09 min) 0.015 max (0.39) seating plane 1 19 36 18 notes: 1. dimensions shown are in inches (mm). 2. lead identification numbers are for reference only. 3. lead cluster shall be centered within 0.01(0.25) of outline dimensions. lead spacing dimensions apply only at seating plane. 4. package is kovar with electroless nickel plating. 5. case is electrically floating. 6. leads are gold coated kovar. figure 19. sd-14595/96/97 mechanical outline 36-pin ddip (kovar) figure 20. sd-14595/96/97 mechanical outline 36-pin flat pack (ceramic) note: lead cluster to be centralized about case centerline within .010 1 18 19 36 .018.002 1.900 (max) .100 (typ) pin numbers are for ref. only 17 eq. sp. @ .100 = 1.700 (tol. noncum) 1 pin 1 denoted by contrasting colored bead or index mark .40 min (typ) .100.010 (typ) .010.002 (typ) .210 (max) .800 (max) side view bottom view table 7. sd-14595/96/97 pinouts function pin function pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 s1(res) s1(syn) ------- s2(res) s2(syn) cos(x) s3(res) s3(syn) sin(x) s4(res) ----------- ------- n/c n/c n/c rl rh vel analog return (v) e inh cb bit 14b (14595 only) lbe gnd 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 +5 v hbe b1 (msb) b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 (lsb) note: (res) means resolver, (syn) means synchro, and (x) means direct.
11 1 3 5 11 15 10 20 t1a 6 t1b 16 s1 s3 s2 xd-1459xd4 s c v 11 3 2 synchro input 1 3 11 15 10 20 t1a 6 t1b 16 s1 s3 s2 xd-1459xd4 s c v 11 3 2 resolver input s4 400 hz resolver transformer t1 21046 or 21047 or 21048 400 hz synchro transformer t1 21044 or 21045 s1 s2 s3 +15 -s -vs 24126 v s3 s2 xd-1459xd5 s c v 11 3 2 synchro input 400 hz ref transformer 21049 60 hz synchro transformer 24126 * s1 +15 v +c gnd t2 rh rh rl 8 9 synchro input rl xd-1459xd4 10 6 +15 v rh rl v -r 24133 +r +15 gnd 9 8 ref input 60 hz ref transformer 24133 rh rl v rh rl 1 xd-1459xd5 5 11 --vs * note: s3 and s1 connections figure 21. transformer connection diagrams
12 bottom views 0.81 max (20.57) 0.30 max (7.62) 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.100 (2.54) typ tol non cum 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.600 (15.24) 0.105 0.005 (2.67 0.13) 1 345 109876 11 12 14 15 20 19 18 17 16 pin numbers for ref only terminals 0.25 0.001 (6.35 0.03) diam 0.125 (3.18) min length solder plated brass t1a t1b 0.100 (2.54) typ tol non cum 1 5 3 6 10 11 15 16 20 t1a t1b synchro input resolver output to converter v (-sin) +sin v (-cos) +cos s1 s3 s2 1 3 6 10 11 15 16 20 t1a t1b resolver input resolver output to converter v (-sin) +sin v (-cos) +cos s1 s3 s2 s4 0.81 max (20.57) 0.30 max (7.62) 0.100 (2.54) typ tol non cum 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.600 (15.24) 0.105 0.005 (2.67 0.13) 123 5 109876 pin numbers for ref. only. dot on top face identifies pin 1. marking includes part number. terminals 0.25 0.001 (6.35 0.03) diam 0.125 (3.18) min length solder plated brass 1.14 max (28.96) case is black and non-conductive 1.14 max (28.96) ? * s1 ? * s3 ? (+15 v) +15 v ? (-r) -s + * * (rh) ? s2 (rl) + * (v) ? v (+r) ? +c (-vs) ? -vs 24126 or (24133) 0.21 0.03 (5.33 0.76) 0.85 0.010 (21.59 0.25) 0.175 0.010 (4.45 0.25) noncumulative tolerance 0.040 0.002 dia. pin. solder plated brass 0.42 (10.67) max. 0.25 (6.35) min. (bottom view) 0.13 0.03 (3.30 0.76) 1 5 6 10 reference input output to converter rh rl rh rl these external transformers are for use with converter modules with voltage follower buffer inputs. 400 hz synchro and resolver transformer diagrams (tia and tib) each transformer consists of two sections, tia and tib 1. mechanical outlines 2. schematic diagrams a. synchro (21044, 21045) b. resolver (21046, 21047, 21048) the mechanical outline is the same for the synchro input transformer (24126) and the reference input transformer (24133), except for the pins. pins for the reference transformer are shown in parenthesis ( ) below. an asterisk (*) indicates that the pin is omitted. 400 hz reference transformer diagrams (t2) 2.schematic diagram 1. mechanical outline 60 hz synchro and reference transformer diagrams figure 22. transformer mechanical outlines (21049)
ordering information xx-1459xxx-xxxx supplemental process requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection k = one lot date code w = one lot date code and precap source y = one lot date code and 100% pull test z = one lot date code, precap source and 100% pull test blank = none of the above accuracy: 2 = 5.2 minutes 4 = 2.6 minutes 5 = 1.3 minutes (16 bit only) process requirements: 0 = standard ddc processing, no burn-in (see table below.) 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in (see table below.) temperature grade/data requirements: 1 = -55c to +125c 2 = -40c to +85c 3 = 0c to +70c 4 = -55c to +125c with variables test data 5 = -40c to +85c with variables test data 8 = 0c to +70c with variables test data input: 1 = 11.8/400 hz (sd and rd only) 2 = 90/400 hz (sd only) 3 = 90/60 hz (sd only) 4 = direct/400 hz (xd only) 5 = direct/60 hz (xd only) package: d = dip f = flat pack (consult factory for availability.) resolution: 5 = programmable (14 or 16 bits) 6 = 14 bit 7 = 16 bit input type: rd = resolver input sd = synchro input xd = direct input 13 *standard ddc processing with burn-in and full temperature test see table below. 1015, table 1 burn-in a 2001 constant acceleration c 1010 temperature cycle a and c 1014 seal 2009, 2010, 2017, and 2032 inspection condition(s) method(s) test mil-std-883 standard ddc processing
14 the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. c-09/98-0 printed in the u.s.a. type freq. ref. voltage l-l voltage ref. xfmr signal xfmr synchro synchro resolver resolver resolver synchro? 400 hz 400 hz 400 hz 400 hz 400 hz 60 hz 115 v 26 v 115 v 26 v 26 v 115 v 90 v 11.8 v 90 v 26 v 11.8 v 90 v 21049 21049 21049 21049 21049 24133-1 24133-3 21045* 21044* 21048* 21047* 21046* 24126-1 24126-3 part numbers * the part number for each 400 hz synchro or resolver isolation transformer includes two separate modules as shown in the outline drawings. ? 60 hz synchro transformers are available in two temperature ranges: 1 = -55c to +105c 3 = 0c to +70c transformer ordering information reference and signal transformers for the voltage follower buffer input converters must be ordered separately from the followin g table: ilc data device corporation registered to iso 9001 file no. a5976 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7389 or 7413 headquarters - tel: (631) 567-5600 ext. 7389 or 7413, fax: (631) 567-7358 southeast - tel: (703) 450-7900, fax: (703) 450-6610 west coast - tel: (714) 895-9777, fax: (714) 895-4988 europe - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 asia/pacific - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com

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